Negative voltage generator for a semiconductor memory device

ABSTRACT

A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

[0001] This application claims priority from Provisional Application No.______, entitled NEGATIVE VOLTAGE GENERATOR IN SEMICONDUCTOR MEMORYDEVICE, filed on May 4, 2001, by the same inventors of the presentapplication, the contents of which are herein incorporated by reference.

BACKGROUND

[0002] 1. Field of the Invention

[0003] The present invention relates generally to semiconductor memorydevices, and more particularly, to a negative voltage generator for asemiconductor memory device.

[0004] 2. Description of the Related Art

[0005] A typical semiconductor memory devices utilizes an accesstransistor in each memory cell to store, read and refresh data in thecell. The refresh time of a memory cell is degraded by the leakagecurrent of the access transistor. A negatively biased word line schemehas been devised to reduce this leakage current. A memory deviceemploying a negative word line scheme applies a negative voltage Vbb orVnn to the word lines of non-selected memory cells. This is alsoreferred to as back biasing the word line.

[0006]FIG. 1 illustrates a prior art negative voltage generator whichincludes an oscillator 100, a negative charge pump 200 and a leveldetector 300. The generator of FIG. 1 has commonly been used to generatea negative voltage (Vbb) for reverse biasing the substrate of asemiconductor device, thereby reducing leakage current. Thus, it isoften referred to as a substrate voltage generator. It generates aregulated negative voltage supply using a negative feedback operation.When Vbb increases due to substrate leakage current, the detector 300enables the oscillator 100 which then drives the charge pump 200. Thevoltage of Vbb is driven more negative by the charge pump until thedetector disables the oscillator.

[0007]FIG. 2 illustrates a typical prior art Vbb level detector 300.When Vbb increases due to substrate leakage current, the source-drainequivalent resistance of M2 (700) increases, thereby causing the voltageof Node A to rise. When node A reaches the trip point of inverter 900,the output signal OUT goes high and enables the oscillator 100 whichthen drives the negative charge pump 200 with a rectangular wave signal.The negative charge pump includes a capacitor 400 and two diodes DGND(500) and DSUB (600) which are arranged in a typical negative chargepumping configuration. When the rectangular signal is high, node B isclamped at one threshold voltage (Vth) above ground by DGND, while theother end of the capacitor 400 is charged to the positive supply voltageVdd. Then, when the rectangular signal goes low, the capacitor pumpsnegative charge to Vbb through DSUB.

[0008] To implement a negatively biased word line scheme, the prior artnegative voltage generator described above with reference to FIGS. 1 and2 has also been utilized to provide the negative bias for the wordlines. However, this prior art generator is not very well suited fordriving negative word lines. The regulator shown in FIGS. 1 and 2 wasoriginally intended to provide a small amount of current for reverse orback biasing a semiconductor substrate. A negative word line scheme,however, requires large current drive capability to discharge a wordline from a boosted voltage of Vpp to the negative voltage of Vbb or Vnnduring a word line precharge operation. These large discharge currentscause fluctuations in the negative voltage supply. The drive circuitryfor a negative word line scheme places additional demands on thenegative voltage generator because it consumes additional operatingcurrent from the negative voltage supply.

[0009] Another problem with the prior art negative voltage generator isthat the voltage gain of the detector 300 is very low (˜0.1), so theresponse time is slow. This causes a long on/off delay time (˜1 μs)which results in a large ripple component in the negative voltage Vbb asshown in FIG. 3. A further problem with the detector is that it ishighly sensitive to process and temperature variations.

SUMMARY

[0010] A negative voltage generator in accordance with the presentinvention is controlled responsive to a word line precharge signal.

[0011] One aspect of the present invention is a negative voltagegenerator for a semiconductor memory device comprising: a first chargepump having an output; and a second charge pump having an output coupledto the output of the first charge pump, wherein the second charge pumpis adapted to be controlled by a word-line precharge signal. Anotheraspect is a method for operating a semiconductor memory devicecomprising controlling a negative voltage generator responsive to a wordline precharge signal.

[0012] Another aspect of the present invention is a level detector for asemiconductor device comprising: a differential amplifier having a firstinput and a second input; a first voltage divider coupled to the firstinput of the differential amplifier; and a second voltage dividercoupled to the second input of the differential amplifier, and adaptedto drive the second input of the differential amplifier responsive to anoutput signal. Another aspect is a method for detecting a voltage in asemiconductor device comprising: dividing a reference signal, therebygenerating a first divided signal; dividing the voltage, therebygenerating a second divided signal; and amplifying the differencebetween the first and second divided signals.

[0013] A further aspect of the present invention is a negative voltageregulator for a semiconductor device comprising: a differentialamplifier having a first input, a second input, and an output; an outputtransistor coupled to the output of the differential amplifier; a firstvoltage divider coupled to the first input of the differentialamplifier; and a second voltage divider coupled to the second input ofthe differential amplifier, and adapted to drive the second input of thedifferential amplifier responsive to an output signal from the outputtransistor. Another aspect is a method for generating a first negativevoltage in a semiconductor device comprising: generating a secondnegative voltage; dividing a reference signal, thereby generating afirst divided signal; dividing the first negative voltage, therebygenerating a second divided signal; amplifying the difference betweenthe first and second divided signals, thereby generating a drive signal;and driving an output transistor coupled between the first negativevoltage and the second negative voltage responsive to the drive signal.

[0014] Yet another aspect of the present invention is a semiconductormemory device having a negative word line scheme comprising a negativevoltage generator comprising: a charge pump adapted to generate a firstnegative voltage, and a negative voltage regulator coupled to thenegative charge pump and adapted to generate a second negative voltageby regulating the first negative voltage. Another aspect is a method fordriving a word line in a semiconductor memory device having a negativeword line scheme comprising: generating a first negative voltage;generating a second negative voltage by regulating the first negativevoltage; and driving the word line with the second negative voltage.

[0015] These and other aspects of the present invention are disclosedand claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a diagram of a prior art negative voltage generator.

[0017]FIG. 2 is a schematic diagram of a prior art level detector.

[0018]FIG. 3 illustrates the operation of a prior art negative voltagegenerator and level detector.

[0019]FIG. 4 is a diagram of an embodiment of a negative voltagegenerator in accordance with the present invention.

[0020]FIG. 5 is a diagram of a second embodiment of a negative voltagegenerator in accordance with the present invention.

[0021]FIG. 6 is a diagram of a third embodiment of a negative voltagegenerator in accordance with the present invention.

[0022]FIG. 7 is a timing diagram of some example word line prechargecommands and signals suitable for use with the present invention.

[0023]FIG. 8 is a schematic diagram of an embodiment of a level detectorin accordance with the present invention.

[0024]FIG. 9 illustrates the operation of an embodiment of a leveldetector in accordance with the present invention.

[0025]FIG. 10 is a schematic diagram of an embodiment of a negativevoltage regulator in accordance with the present invention.

[0026]FIG. 11 illustrates the operation of an embodiment of a negativevoltage regulator in accordance with the present invention.

DETAILED DESCRIPTION

[0027] Negative Voltage Generator

[0028]FIG. 4 is a diagram of an embodiment of a negative voltagegenerator in accordance with the present invention. The embodiment ofFIG. 4 includes an oscillator 10, a first negative charge pump 20 havingan output Vbb, and a level detector 30 arranged as in the prior art.However, the embodiment of FIG. 4 further includes a second negativecharge pump 50 having an output coupled to the output of the firstnegative charge pump 20, either through a Vnn generator 40 as shown inFIG. 4, or through a direct connection as shown in FIGS. 5 and 6, orthrough any other suitable arrangement. The second negative charge pump50 (also referred to as a “kicker”) is activated and supplies additionalnegative charge for shutting off a word line responsive to a prechargecommand or signal. The second negative charge pump is preferablydesigned to provide an accurately pre-determined amount of negativecharge. Thus, by providing most of the precharge current required toshut off a word line, the second charge pump dramatically reducesvoltage fluctuations on the negative voltage supply.

[0029] In a preferred embodiment, the second charge pump is constructedessentially the same as the first charge pump, but it is activatedresponsive to a precharge command or signal. The capacitor in the secondcharge pump is preferably sized to discharge just the right amount ofcharge from a word line during a precharge operation.

[0030] Since most semiconductor memory devices operate from positivepower supplies that are referenced to a power supply ground, a back biasscheme is described in terms of a negative voltage. However, as usedherein, negative is understood to mean simply the reverse polarity fromthat applied to a word line during an access operation.

[0031] The level detector 30 performs the same function as the leveldetector 300 in FIG. 1, but in a preferred embodiment, it is replacedwith a detector having faster response time and greater immunity toprocess and temperature variations in accordance with the presentinvention such as that shown in FIG. 8 below.

[0032] The embodiment shown in FIG. 4 further includes an optional Vnngenerator 40 which is a voltage regulator that generates Vnn bycanceling ripple in Vbb. Thus, a more stable negative word line bias canbe obtained using the Vnn supply. A preferred embodiment of a negativevoltage regulator is described below with respect to FIGS. 10 and 11. Anadvantage of using a negative voltage regulator in accordance with thepresent invention is that it cancels ripple in Vbb. Thus, it provides amore stable negative word line bias. Another advantage is that, sinceVnn (typically about −0.5 Volts) is less negative than Vbb (typicallyabout −1.0 Volts), it reduces the total amount of charge that must beremoved from a word line during a precharge operation. A furtheradvantage of using a negative voltage regulator to reduce the negativeword line bias voltage is that the drive circuitry for the negative wordline driving scheme dissipates less power.

[0033] Examples of precharge commands and signals suitable fortriggering the second negative charge pump are shown in FIG. 7 which isa timing diagram of commands and signals for a Synchronous DynamicRandom Access Memory (SDRAM) device. Precharge commands are typicallyexternal commands such as Row Precharge, Auto Precharge, All BanksPrecharge, etc. Signals are typically internal signals such as PR inFIG. 7. The present invention, however, is not limited use with thesecommands and signals, or to SDRAM devices. The present invention can beadapted to work with any other suitable commands and/or signals thatanticipate or correspond to a precharge operation for a word line.Pprecharge command and signal will be used interchangeably. Thus,precharge command or signal is understood to refer to any suitablecommand and/or signal that anticipates or corresponds to a prechargeoperation for a word line. Moreover, the present invention is notlimited to use with word lines, but can also be used with any other typeof memory access line the operates with a negative precharge voltage.

[0034]FIG. 5 is a diagram of another embodiment of a negative voltagegenerator in accordance with the present invention. In the embodiment ofFIG. 5, there is no negative voltage regulator, and the output of thesecond negative charge pump 50 is connected directly to the output ofthe first negative charge pump 20. In this configuration, Vbb and Vnnare the same signal, and the second charge pump is designed to deliverthe predetermined negative charge directly to the word line controlcircuit in response to a word line precharge command or signal.

[0035]FIG. 6 is a diagram of a third embodiment of a negative voltagegenerator in accordance with the present invention. The embodiment ofFIG. 6 is the same as the embodiment of FIG. 5 except that it includes anegative voltage regulator 40 which has an input coupled to the outputsof the first and second charge pumps, and an output that generates theregulated Vnn signal.

[0036] Level Detector

[0037]FIG. 8 is a schematic diagram of an embodiment of a level detectorin accordance with the present invention. The level detector of FIG. 8includes a first voltage divider formed from resistors R1 and R2, asecond voltage divider formed from resistors R3 and R4, a differentialamplifier formed from transistors MP2, Mp2, Mp3, Mn1, and Mn2, and oneor more inverters INV1, INV2. The first divider is connected between aninternal reference voltage Vref and a power supply ground. The seconddivider is connected between the internal reference voltage Vref and thenegative power supply, in this case Vbb. The voltage dividers divide thevoltage between Vref and ground and between Vref and Vbb, therebygenerating two divided signals X and Y which operate as comparisonsignals in response to Vref and Vbb according to the followingequations:$X = {{{{Vref} \cdot \frac{R2}{{R1} + {R2}}}\quad {and}\quad Y} = {\left( {{Vref} - {Vbb}} \right) \cdot \frac{R4}{{R3} + {R4}}}}$

[0038] Vref is a stable reference voltage, so X has a constant value,and the output Z will depend on whether Y is higher or lower than X. Thetarget level for Vbb is given by:${Vbb} = {{Vref} \cdot \frac{{R2R3} - {R1R4}}{{R1R3} + {R2R3}}}$

[0039] Transistors Mp1, Mp2, Mp3, Mn1, and Mn2 are arranged as adifferential amplifier with Mp3 forming a current source that biases Mp1and Mp2 which are arranged as a differential pair of input transistors.Transistors Mn1 and Mn2 are arranged as a current mirror load referencedto the power supply ground. The output Z is taken from the connectionbetween the drains of Mp1 and Mn1 and applied to the input of inverterINV1.

[0040] Since the differential amplifier has a high voltage gain(typically about 50), the output Z will swing quickly past the switchingpoint of inverter INV1 as Y swings above and below X. The high gaincharacteristic of the differential amplifier reduces the on/off delay ofthe detector as shown in FIG. 9. This, in turn, reduces fluctuations inthe negative voltage supply.

[0041] Another advantage of the level detector shown in FIG. 8 is thatthe resistor divided voltage levels X and Y are insensitive to processand temperature variations, so the detector is also insensitive to thesevariations.

[0042] A further advantage is that, by connecting the voltage dividersto Vref instead of a positive power supply such as Vdd or a boostedvoltage source such as Vpp, the level detector can be made insensitiveto variations in the supply voltage, as happens, for example when Vdd isincreased during a testing operation.

[0043] Yet another advantage of the level detector shown in FIG. 8 isthat the current mirror load is referenced to the power supply groundterminal rather than the Vbb terminal. This reduces the current drawfrom Vbb.

[0044] An additional advantage is that the comparison signals X and Yare biased by the voltage dividers at a quiescent voltage that is wellabove Vbb. This simplifies the design of the differential amplifier. Inessence, the voltage dividers level shift the Vbb signal to a convenientvoltage level.

[0045] A level detector in accordance with the present invention can besubstituted anywhere for the conventional level detector shown in FIG. 2and is not limited to applications using a negative word line scheme.

[0046] Negative Voltage Regulator

[0047]FIG. 10 is a schematic diagram of an embodiment of a negativevoltage regulator (Vnn generator) in accordance with the presentinvention. The regulator of FIG. 10 includes a first voltage dividerformed from resistors R5 and R6, a second voltage divider formed fromresistors R7 and R8, a differential amplifier formed from transistorsMp1, Mp2, Mp3, Mn1, and Mn2, and an output transistor Mn3.

[0048] The first divider is connected between an internal referencevoltage Vref and a power supply ground. The second divider is connectedbetween the internal reference voltage Vref and the drain of transistorMn3. The source of Mn3 is connected to the negative power supply Vbb,and the gate of Mn3 is connected to the output of the differentialamplifier at node G between the drains of Mn1 and Mp1.

[0049] Transistors Mp1, Mp2, Mp3, Mn1, and Mn2 are arranged as adifferential amplifier with Mp3 forming a current source that biases Mp1and Mp2 which are arranged as a differential pair of input transistors.Transistors Mn1 and Mn2 are arranged as a current mirror load referencedto the negative power supply Vbb.

[0050] The voltage dividers divide the voltage between Vref and groundand between Vref and Vnn, thereby generating two divided signals A and Bwhich operate as comparison signals in response to Vref and Vnn. Sincethe regulator is connected in a negative feedback arrangement, thevoltages on nodes A and B are forced to the same value. Thus, Vnn isgiven by the following equation:${Vnn} = {{Vref} \cdot \frac{{R6R7} - {R5R8}}{{R5R8} + {R6R8}}}$

[0051] As the voltage of Vbb varies, the voltage at node G tracks in thesame phase as Vbb so that the gate-to-source voltage of Mn3 remainsconstant and the Vbb ripple caused by the detector on/off time iscancelled at Vnn as shown in FIG. 11.

[0052] An advantage of the negative voltage regulator of FIG. 10 is thatthe voltage dividers bias the comparison signals A and B at a quiescentvoltage that is well above Vnn. This greatly simplifies the regulatorcircuit as compared to other regulators which typically have comparisonsignals that are biased at about the same voltage level as Vnn. Inessence, the voltage dividers level shift the signals to a convenientvoltage level.

[0053] Having described and illustrated the principles of the inventionin some preferred embodiments thereof, it should be apparent that theinvention can be modified in arrangement and detail without departingfrom such principles. We claim all modifications and variations comingwithin the spirit and scope of the following claims.

1. A negative voltage generator for a semiconductor memory devicecomprising: a first charge pump having an output; and a second chargepump having an output coupled to the output of the first charge pump,wherein the second charge pump is adapted to be controlled by aprecharge signal.
 2. A negative voltage generator according to claim 1further comprising a negative voltage regulator having an input coupledto the output of the first charge pump and an output coupled to theoutput of the second charge pump.
 3. A negative voltage generatoraccording to claim 1 wherein the output of the first charge pump isconnected directly to the output of the second charge pump.
 4. Anegative voltage generator according to claim 3 further comprising anegative voltage regulator having an input coupled to the outputs of thefirst and second charge pumps.
 5. A negative voltage generator accordingto claim 1 further comprising a level detector having an input coupledto the output of the first negative charge pump.
 6. A negative voltagegenerator according to claim 1 wherein the precharge signal is aword-line precharge signal.
 7. A negative voltage generator for asemiconductor memory device comprising: first means for pumping chargeto a negative voltage source; and second means for pumping charge to thenegative voltage source, wherein the second means for pumping charge isadapted to be controlled by a precharge signal.
 8. A negative voltagegenerator according to claim 7 wherein the first means for pumpingcharge has an output connected directly to an output of the second meansfor pumping charge.
 9. A negative voltage generator according to claim 7further comprising means for regulating the negative voltage source. 10.A negative voltage generator according to claim 9 wherein: the firstmeans for pumping charge has an output connected directly to an outputof the second means for pumping charge; and the means for regulating thenegative voltage source has in input coupled to an output of the firstmeans for pumping charge and an output of the second means for pumpingcharge.
 11. A negative voltage generator according to claim 9 whereinthe means for regulating the negative voltage source has in inputcoupled to an output of the first means for pumping charge and an outputcoupled to an output of the second means for pumping charge.
 12. Anegative voltage generator according to claim 7 further comprising meansfor detecting the voltage level of the negative voltage source.
 13. Anegative voltage generator according to claim 7 wherein the negativevoltage source is a negative voltage source for negatively biasing aword line.
 14. A negative voltage generator for a semiconductor memorydevice comprising: an oscillator; a first charge pump having an inputcoupled to the oscillator and an output for generating a first negativevoltage responsive to an oscillating signal from the oscillator; anegative voltage regulator having an input coupled to the output of thenegative voltage generator and an output for generating a secondnegative voltage responsive to the first negative voltage; and a secondcharge pump having an output coupled to the output of the negativevoltage regulator, wherein the second charge pump is adapted to becontrolled by a word-line precharge signal.
 15. A negative voltagegenerator according to claim 14 further comprising a level detectorhaving an input coupled to the output of the first charge pump and anoutput coupled to the oscillator.
 16. A negative voltage generatoraccording to claim 14 wherein the second charge pump is adapted to pumpa predetermined amount of charge to the second negative voltageresponsive to the word-line precharge signal.
 17. A method for operatinga semiconductor memory device comprising controlling a negative voltagegenerator responsive to a precharge signal.
 18. A method according toclaim 17 wherein: the negative voltage generator comprises a firstcharge pump and a second charge pump; and controlling a negative voltagegenerator responsive to a precharge signal comprises activating thesecond charge pump responsive to the precharge signal.
 19. A methodaccording to claim 18 wherein the first charge pump generates a firstnegative voltage.
 20. A method according to claim 19 wherein activatingthe second charge pump responsive to the precharge signal comprisescoupling charge from the second charge pump to the first negativevoltage.
 21. A method according to claim 19 further comprisingregulating the first negative voltage, thereby generating a secondnegative voltage.
 22. A method according to claim 21 wherein activatingthe second charge pump responsive to the precharge signal comprisescoupling charge from the second charge pump to the second negativevoltage.
 23. A method according to claim 18 wherein activating thesecond charge pump responsive to the precharge signal comprisessupplying a predetermined amount of charge from the second charge pump.24. A method according to claim 17 wherein the precharge signal is aword-line precharge signal.
 25. A negative voltage level detector for asemiconductor device comprising: a differential amplifier having a firstinput and a second input; a first voltage divider coupled to the firstinput of the differential amplifier; and a second voltage dividercoupled to the second input of the differential amplifier, and adaptedto drive the second input of the differential amplifier responsive to anegative voltage.
 26. A negative voltage level detector according toclaim 25 wherein the first voltage divider is adapted to drive the firstinput of the differential amplifier responsive to a reference voltage.27. A negative voltage level detector according to claim 26 wherein thefirst voltage divider comprises: a first resistor coupled between thereference voltage and the first input of the differential amplifier; anda second resistor coupled between the first input of the differentialamplifier and a power supply terminal.
 28. A negative voltage leveldetector according to claim 26 wherein the second voltage dividercomprises: a first resistor coupled between a reference voltage and thesecond input of the differential amplifier; and a second resistorcoupled between the second input of the differential amplifier and thenegative voltage.
 29. A negative voltage level detector according toclaim 25 further comprising an inverter having an input coupled to anoutput of the differential amplifier.
 30. A negative voltage leveldetector according to claim 25: wherein the first voltage dividercomprises: a first resistor coupled between a reference voltage and thefirst input of the differential amplifier, and a second resistor coupledbetween the first input of the differential amplifier and a power supplyterminal; wherein the second voltage divider comprises: a third resistorcoupled between the reference voltage and the second input of thedifferential amplifier, and a fourth resistor coupled between the secondinput of the differential amplifier and the negative voltage; whereinthe differential amplifier comprises: a differential pair of inputtransistors coupled to the first and second input terminals, a currentsource coupled to the differential pair of transistors, and a loadcoupled to the differential pair of transistors; and further comprisingan inverter having an input coupled to an output of the differentialamplifier.
 31. A negative voltage level detector according to claim 25wherein the differential amplifier comprises a current mirror loadcoupled to a power supply terminal.
 32. A negative voltage leveldetector according to claim 25 wherein: the semiconductor device is amemory device utilizing a negative word line scheme; and the negativevoltage is a negative voltage source for negatively biasing a word line.33. A negative voltage level detector for a semiconductor devicecomprising: means for dividing a reference voltage, thereby generating afirst divided signal; means for dividing a negative voltage, therebygenerating a second divided signal; and means for amplifying thedifference between the first and second divided signals.
 34. A negativevoltage level detector according to claim 33 wherein the means fordividing a reference voltage comprises: a first resistor coupled betweenthe reference voltage and a first input of the means for amplifying; anda second resistor coupled between the first input of the means foramplifying and a power supply terminal.
 35. A negative voltage leveldetector according to claim 33 wherein the means for dividing a negativevoltage comprises: a first resistor coupled between a reference voltageand a second input of the means for amplifying; and a second resistorcoupled between the second input of the means for amplifying and thenegative voltage.
 36. A negative voltage level detector according toclaim 33 wherein the means for amplifying comprises a differentialamplifier referenced to a power supply voltage.
 37. A negative voltagelevel detector according to claim 33 wherein: the semiconductor deviceis a memory device utilizing a negative word line scheme; and thenegative voltage is a negative voltage for biasing a word line.
 38. Anegative voltage level detector for a semiconductor device comprising: adifferential amplifier having a first input and a second input; a firstvoltage divider coupled to the first input of the differential amplifierand adapted to drive the first input of the differential amplifierresponsive to a reference voltage, wherein the first voltage divider isadapted to maintain the first input of the differential amplifier at apositive voltage; and a second voltage divider coupled to the secondinput of the differential amplifier and adapted to drive the secondinput of the differential amplifier responsive to a negative voltage,wherein the second voltage divider is adapted to maintain the secondinput of the differential amplifier at a positive voltage.
 39. Anegative voltage level detector according to claim 38 wherein the firstvoltage divider comprises: a first resistor coupled between thereference voltage and the first input of the differential amplifier; anda second resistor coupled between the first input of the differentialamplifier and a power supply terminal.
 40. A negative voltage leveldetector according to claim 38 wherein the second voltage dividercomprises: a first resistor coupled between a reference voltage and thesecond input of the differential amplifier; and a second resistorcoupled between the second input of the differential amplifier and thenegative voltage.
 41. A method for detecting a negative voltage in asemiconductor device comprising: dividing a reference voltage, therebygenerating a first divided signal; dividing the negative voltage,thereby generating a second divided signal; and amplifying thedifference between the first and second divided signals.
 42. A methodaccording to claim 41 wherein dividing the reference voltage compriseslevel shifting the reference voltage.
 43. A method according to claim 41wherein dividing the negative voltage comprises level shifting thenegative voltage.
 44. A method according to claim 41 wherein amplifyingthe difference between the first and second divided signals comprisesreferencing a differential amplifier to a power supply voltage.
 45. Amethod according to claim 41 wherein: the semiconductor device is amemory device utilizing a negative word line scheme; and the negativevoltage is a negative voltage for biasing a word line.
 46. A negativevoltage regulator for a semiconductor device comprising: a differentialamplifier having a first input, a second input, and an output; an outputtransistor coupled to the output of the differential amplifier andarranged to generate a second negative voltage from a first negativevoltage; a first voltage divider coupled to the first input of thedifferential amplifier; and a second voltage divider coupled to thesecond input of the differential amplifier, and adapted to drive thesecond input of the differential amplifier responsive to the secondnegative voltage.
 47. A negative voltage regulator according to claim 46wherein the first voltage divider is adapted to drive the first input ofthe differential amplifier responsive to a reference voltage.
 48. Anegative voltage regulator according to claim 47 wherein the firstvoltage divider comprises: a first resistor coupled between thereference voltage and the first input of the differential amplifier; anda second resistor coupled between the first input of the differentialamplifier and a power supply terminal.
 49. A negative voltage regulatoraccording to claim 46 wherein the second voltage divider comprises: afirst resistor coupled between a reference voltage and the second inputof the differential amplifier; and a second resistor coupled between thesecond input of the differential amplifier and the second negativevoltage.
 50. A negative voltage regulator according to claim 46: whereinthe first voltage divider comprises: a first resistor coupled between areference voltage and the first input of the differential amplifier, anda second resistor coupled between the first input of the differentialamplifier and a power supply terminal; wherein the second voltagedivider comprises: a third resistor coupled between the referencevoltage and the second input of the differential amplifier, and a fourthresistor coupled between the second input of the differential amplifierand a the second negative voltage; wherein the differential amplifiercomprises: a differential pair of input transistors coupled to the firstand second input terminals, a current source coupled to the differentialpair of transistors, and a load coupled to the differential pair oftransistors; and wherein the output transistor has a second terminalcoupled to an output terminal of the differential amplifier.
 51. Anegative voltage regulator according to claim 46 wherein: thesemiconductor device is a memory device utilizing a negative word linescheme; and the second negative voltage is a negative voltage source fornegatively biasing a word line.
 52. A negative voltage regulator for asemiconductor device comprising: means for generating a second negativevoltage from a first negative voltage responsive to a drive signal;means for dividing a reference voltage, thereby generating a firstdivided signal; means for dividing the second negative voltage, therebygenerating a second divided signal; means for amplifying the differencebetween the first and second divided signals, thereby generating thedrive signal.
 53. A negative voltage regulator according to claim 52wherein the means for dividing the reference voltage comprises: a firstresistor coupled between the reference voltage and a first input of themeans for amplifying; and a second resistor coupled between the firstinput of the means for amplifying and a power supply terminal.
 54. Anegative voltage regulator according to claim 52 wherein the means fordividing the second negative voltage comprises: a first resistor coupledbetween a reference voltage and the second input of the means foramplifying; and a second resistor coupled between the second input ofthe means for amplifying and the second negative voltage.
 55. A negativevoltage regulator according to claim 52 wherein: the semiconductordevice is a memory device utilizing a negative word line scheme; and thefirst negative voltage is a negative voltage for biasing a word line.56. A negative voltage regulator for a semiconductor device comprising:a differential amplifier having a first input, a second input, and anoutput; an output transistor coupled to the output of the differentialamplifier and arranged to generate a second negative voltage from afirst negative voltage; a first voltage divider coupled to the firstinput of the differential amplifier and adapted to drive the first inputof the differential amplifier responsive to a reference voltage, whereinthe first voltage divider is adapted to maintain the first input of thedifferential amplifier at a positive voltage; and a second voltagedivider coupled to the second input of the differential amplifier andadapted to drive the second input of the differential amplifierresponsive to the second negative voltage, wherein the second voltagedivider is adapted to maintain the second input of the differentialamplifier at a positive voltage.
 57. A negative voltage level detectoraccording to claim 56 wherein the first voltage divider comprises: afirst resistor coupled between the reference voltage and the first inputof the differential amplifier; and a second resistor coupled between thefirst input of the differential amplifier and a power supply terminal.58. A negative voltage level detector according to claim 56 wherein thesecond voltage divider comprises: a first resistor coupled between areference voltage and the second input of the differential amplifier;and a second resistor coupled between the second input of thedifferential amplifier and the second negative voltage.
 59. A method forgenerating a first negative voltage in a semiconductor devicecomprising: generating a second negative voltage; dividing a referencevoltage, thereby generating a first divided signal; dividing the firstnegative voltage, thereby generating a second divided signal; amplifyingthe difference between the first and second divided signals, therebygenerating a drive signal; and driving an output transistor coupledbetween the first negative voltage and the second negative voltageresponsive to the drive signal.
 60. A method according to claim 59wherein dividing the reference voltage comprises level shifting thereference voltage.
 61. A method according to claim 59 wherein dividingthe first negative voltage comprises level shifting the first negativevoltage.
 62. A method according to claim 59 wherein amplifying thedifference between the first and second divided signals comprisesreferencing a differential amplifier to the second negative voltage. 63.A method according to claim 59 wherein: the semiconductor device is amemory device utilizing a negative word line scheme; and the firstnegative voltage is a negative voltage for biasing a word line.